One area of material processing in the semiconductor industry which presents formidable challenges is, for example, the manufacture of integrated circuits (ICs). Demands for increasing the speed of ICs in general, and memory devices in particular, force semiconductor manufacturers to make devices smaller and smaller on the substrate surface. Moreover, in order to reduce fabrication costs, it is necessary to reduce the number of steps (e.g., etch steps, deposition steps, etc.) required to produce an IC structure and, hence, reduce the overall complexity of the IC structure and the fabrication methods thereof. These demands are further exacerbated by both the reduction in feature size and the increase of substrate size (i.e., 200 mm to 300 mm and greater), which places greater emphasis on critical dimensions (CD), process rate and process uniformity to maximize the yield of superior devices. through inter-level dielectric layers. Usually, an etch stop layer is placed under a dielectric layer in order to protect the underlying layers (devices) from being damaged during over-etching. An etch stop layer generally includes a material that when exposed to the chemistry utilized for etching the dielectric layer has an etch rate less than the dielectric layer etch rate (i.e., the etch chemistry has a high etch selectivity to the dielectric layer relative to the etch stop layer). Furthermore, the etch stop layer provides a barrier for permitting an over-etch step to assure that all features on the substrate are etched to the same depth.
However, the etch stop layer complicates the process integration, increases manufacturing cost and decreases device performance. Without an etch stop layer, etch depth can vary depending on etch rate (ER) since fixed-time recipes are used. Since, for example, the etch tool is subject to equipment disturbance, the etch rate can change significantly over maintenance cycles. In order to maintain a constant etch rate, frequent tool qualification and maintenance procedures are required. Therefore, in-situ estimation of the etch rate can determine whether the process chamber is in a normal condition and can provide information to control the etch time so that the etch depth is on target.